Today's computer and server designs are very complex from a hardware architecture perspective. The processor designs utilize both internal and external busses/fabric. This presents a significant challenge and cost to the business when testing each subassembly and achieving 100% functional test coverage. For example, if a backplane that holds several processor assemblies is used for testing, the cost of providing the backplane and the processor assemblies may be high and testing may be very complex due to the large number of processor assemblies that may have problems. If known good processor assemblies are used while a single processor assembly is under test, the cost of testing and providing the known good processor assemblies may be very large. The testing may also be cumbersome and lengthy.